Digital phase locked loops conventionally are utilized to capture and lock in on incoming data signals. The digital phase locked loops generally attempt to generate a data clock which has a data pulse sampling edge which occurs at a midpoint between the two data edges which bound a data bit. By selecting the midpoint of the data bit, a maximum sampling timing margin is provided.
The digital phase locked loop typically generates the data clock sampling edge a fixed number of local oscillator clock pulses following a sensed data pulse transition edge. This is based upon a predetermined presumption of the data pulse width. If sampling asymmetrical data (data one's and data zero's having different widths), the timing margin to the data pulse edge following the sampling clock pulse edge is reduced as the data bit width becomes more narrow. If the asymmetrical data pulse bit width narrows to less than fifty (50) percent of the expected or presumed pulse width, then the data pulse cannot be correctly recovered by the fixed data pulse clock.
It would be desirable to provide a digital phase locked loop which can recover a wide range of data pulse widths without undue loss of stability.